A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result.

A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted.

To handle floating point operations a floating point status unit and a floating point control unit are provided within the translator.

By appending tag values to each floating point number, the floating point unit can quickly determine which floating point numbers are special floating point numbers and the type of special floating point number.

A floating point unit includes a floating point adder to perform a floating point addition operation between first and second floating point numbers each having an exponent and a mantissa.

floating point operations per second (FLOPS)

peak floating point calculating rate

peak floating point calculating rate

The tag value indicates whether the corresponding floating point number is a normal floating point number or a special floating point number.

These recurrences are shown to implement floating point multiplication when applied to serial floating point operands.

Note Y: For the CE that does not implement FP add or FP multiply, but that performs FP divide

Note Y: For the CE that does not implement FP add or FP multiply, but that performs FP divide

Each FP-only CE (Rfp

Each FP-only CE (Rfp

An embodiment of the present invention is a technique to perform mixed mode floating-point (FP) operations and extended FP functions.