The digitized IF signal and the digitized samples of a third signal at the nominal frequency of the first signal at maximum amplitude converted to the IF are correlated.

A Phase Locked Loop (PLL) phase-locks a second LO signal to an IF carrier component of the IF signal.

The downconversion means (32) receives an RF signal and downconverts the RF signal to an in-phase IF signal (IFI) and a quadrature-phase IF signal (IFQ).

A signal processor (35) equalizes and demodulates the IF signal to recover the transmitted signal.

A second demodulator (60) is operative to generate a second demodulated signal corresponding to the second IF signal.

The digital IF signal is down-converted to a received code signal.

A first demodulator (50) is operative to generate a first demodulated signal corresponding to the first IF signal.

Since an output of an IF signal output adder (52) can be used as an IF signal, it is possible to perform calibration without interrupting the modulation operation.

A variable gain amplifier amplifies a first IF signal.

The filter compensation is switched off if a predetermined bounce in the IF signal and/or in one of the signals encompassing the lower LF range is exceeded.

The first IF signal is then mixed with the second LO signal by a second mixer (124) where a second IF signal is produced which is preferably at zero frequency.

An analog-to-digital converter module converts the first IF signal to a digital baseband signal.

Also prior to storage, the IF signal is corrected for a frequency offset signal.

A second tuner (20) is operative to generate a second IF signal corresponding to a second RF signal.

A limiter (122) provides a limited IF signal to the counter (136).