loss of multiframe signal

framing signal with balance bit

A method for diagnosis of the interlock detector (2) and/or the interlock generator (10) of an interlock system (60) is also claimed.

As the client signal is identified within said generic framing procedure signal only a generic framing signal Ethertype is required.

An electronic controller receives the locking signal and the throttle signal, and controls operation of the engine at least partially based on the throttle signal and the locking signal.

The input buffer circuitry uses a single latch signal.

An electronic controller receives the locking signal and the throttle signal, and controls operation of the engine at least partially based on the throttle signal and the locking signal.

The loop filter includes a first low-pass filter (130) configured to receive the charge and lock signals, alter a filter characteristic in response to the lock signal, and provide a first filter signal.

The receiver (202) monitors the downlink signal (212) to identify the frame alignment signal (232).

The equalizer includes a lock detector (20) having an output for providing a lock signal indicative of equalizer convergence.

When the ramp voltage signal is greater than the reference current, an output latch signal is toggled.

The latch signal delay circuit (4) outputs latch signals (LS1-LS8) to the respective source drivers (SD1-SD8).

Said locking signal may be a radio signal, an electric or electronic signal, or a mechanical signal.

The invention includes an actuator actuating when a locking signal is forwarded.

A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal.