The transmitter circuit generates an early timing signal, a nominal timing signal, and a late timing signal.
A timing module generates a first priority timing signal or a second priority timing signal based on a clock signal.
The coarse timing generator (404) generates the coarse timing signal from a clock signal (416) and a timing command input (420).
The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.
The second timing signal is delayed from the first timing signal according to a test parameter.
The accelerating portion or the decelerating portion of the first heart rate signal is replaced with the average heart rate signal to produce a second heart rate signal.
A first heart rate signal is acquired.
An average heart rate signal is acquired.
Estimating a frequency of a sampled cardiac rhythm signal and classifying the rhythm.
Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip.
The fine timing generator (408) includes a sinusoidal-signal generator (504) that receives the clock signal and generates a sinusoidal signal.
The signal for preventing phase over-compensation is mixed with the phase signal to generate the recovered clock signal.
One rate of the sampling clock is a function of a timing signal (160) applied to the timing recovery circuit (107).
The gain adjustment timing at which to change the attenuation amount is made different, on the basis of a gain adjustment timing signal from a timing adjusting unit (112), for each transmission of the pulse signal.
Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system.
The nominal timing signal and the encoded output signal are transmitted through the transmission lines to the receiver circuit.
The selecting and switching circuitry further operating to switch the ACTIVE and INACTIVE timing signal designations and output timing reference signal in response to detecting a fault or a clock switching command.
A second shift register (130) receives a second phase of the random sequence and the rhythm signal produced by the rhythm oscillator (102).
A multiplexer circuit selects between the early and the late timing signals based on a data signal to generate an encoded output signal that encodes the data signal.
Particular criteria for selecting the frequencies for the timing reference signal are disclosed.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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