The address signal or the internal address signal is selectively supplied to the memory device (13) depending on whether the address signal is correct or wrong.
In addition, a radial push-pull signal having gain controlled based on the address signal is given to an address detection circuit (42), and the address signal is detected.
A semiconductor memory device includes address signal level shifters configured to transform a low level address signal into a higher level address signal.
Each decoder generates an enable signal upon receiving of its associated address signal.
A secondary address signal (52), derived from a previous address signal, is provided to each of the plurality of output ports (44).
The address signal is processed in order to determine whether or not it is sufficient in order to automatically sort and distribute the item, and a further address signal may be derived.
Each of the first and second drop generators is configured to receive address signals from a common address source.
A first decoder decodes a first address signal and selects one of the column lines.
Time diversity reception is applied to both the address signal and message signal constituting a call signal.
The memory also includes a buffer circuit which latches the output of the address counter in response to the falling edge of the column address signal.
A selector selects a first address signal for selecting a word line in the first period, and selects a second address signal for selecting a plate line in the second period.
The registered address signal provides at least a true and a complement signal, with the true and complement signal set to approximately the same logical value upon assertion of the reset signal.
The address is changed in response to a rising edge of a column address signal (CAS*).
There is a transition detector (300-308, 319-325) for each address signal.
An optical head (26) reads the wobbling signals and an address detecting circuit (4) detects an address signal multiplexed with the wobbling signals.
The radio link is established by means of a transmission protocol comprising a plurality of data packet groups (PGi), and the data packet groups each contain the address signal and the status signal in a repeated temporally successive form.
Device (36) provides a second telephone number address signal to access address processing unit (38) via telephone network (16).
An address reading section 302 reads the address signal from the phase of one of the optical packets output from the optical splitter section 301.
Signals (digital sine wave signals) (Sd) stored in a memory means (3) are read.
The selective call device receives the information address signal when activated to do so in response to the prompt.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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