An example first data strobe signal is a read data strobe signal provided by the memory.
The data strobe signal follows, by a predetermined delay, the column access strobe signal, and therefore any skew in the column address strobe signal is inherently included within the data strobe signal.
The strobe signal driver circuit is coupled to generate a strobe signal at an intermediate point of the cycle to allow latching of the first signal triggered by the strobe signal.
In another example, the first data strobe signal is a write data strobe signal received by the memory.
The selector receives the input signal, the combined signal, and a repetitive strobe signal, and selects either the input signal or the combined signal to produce an encoded signal based upon a value of the repetitive strobe signal.
The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).
In one embodiment, the device includes a sampling signal generator (202) to generate a sampling signal (208) and a modulation unit (102) operatively coupled to the sampling signal generator (202).
This pulsed sampling signal is used to sample and hold the focus error signal during the time that the pulsed sampling signal is active.
A sampling signal generation unit (106) outputs a sampling signal each time the counter (105) completes one round of count.
A second digital sampling unit (113b) carries out the sampling of the second binarized signal output by the second comparator (112b) to generate a second sampling signal.
A first digital sampling unit (113a) carries out the sampling of the first binarized signal output by the first comparator (112a) to generate a first sampling signal.
According to the invention, the sampling signal (121; 122) consists of a periodic sequence of sampling pulses and pause times.
The sampling signal is thus locked to the reference signal with a phase displacement of 2x.
The control means include sample and hold means (40) for sampling and holding the measurement signal (FE) in response to a sample signal (SCNTRL).
The identification of the received signal and the orientation of the aerial beams are carried out during the reception of the calibration signal.
The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal.
A digital phase shifter capable of shifting the phases of data row by steps shorter than the sampling period even though the sampling signal the phase of which is fixed or a clock signal is used.
When the sampling signal (ECHi) is applied on one of the sampling-holding circuits, an opposite compensation level (V3) lower than the sampling signal level is applied on the N-1 sampling-holding circuits.
The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal.
The receiver generates a sample signal in response to the samples which indicates distance to the object causing the reflections.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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