A resetting device (328) allows the various mechanisms and devices to be reset to zero.
The counter (16) increments while enabled until cleared.
Responsive to the detection of a clearing point for the second thread, a functional unit within the multithreaded processor is cleared of data for both the first and the second threads.
Pixel reset logic resets the photosensor in accordance with the reset state and an externally applied reset signal.
The reset signal may be fed to the reset input.
The reset module generates an internal reset signal in response to a system reset signal.
A reset circuit produces a composite reset signal, in dependence upon a supply voltage, from reset signals produced by three reset units.
Each reset channel comprises in series a reset circuit (11, 21) generating a reset signal when the reset switch (3) has been closed and opened.
The reset signal is for resetting the integrator (104,106) circuitry.
Erasing/resetting OBD information by a scan-tool
general totalisation indicating device (without zero-resetting device)
A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device.
partial totalisation indicating device (with zero-resetting device)
The reset module holds the internal reset signal for a selected amount of time, and then releases the clock module from the reset clock signal.
The reset line (Reset Output) is then released, after a short time delay (2νsec. delay) so as to not interfere with any succeeding reset line.
A dial indicator that presents the position of a measuring probe (4) on a display (6) The measured value can be defined relative to a zeroing point and the dial indicator includes a zeroing initiator (3) used to initiate zeroing of the position.
The first subfield includes a reset period, a pre-reset period that immediately precedes the reset period, an address period and a sustain period.
The reset transistor has a first terminal coupled to the second terminal of said photosensor, a second terminal coupled to a reset potential, and a third terminal coupled to a reset line.
The ramp reset voltage is applied to all reset amplifiers of all pixels at the same time, thereby providing for reset of the entire array at the same time, i.e., global reset.
A reset stage produces a first reset signal that terminates the first signal pulse and a second reset signal that terminates the second signal pulse.
The output optical return-to-zero signal is an optical differential return-to-zero signal, and the output optical return-to-zero signal is substantially free from any frequency chirp.
The self-zeroing control unit (3) provides for a self zeroing operation mode and a normal operation mode.
A decision feedback equalizer is suitable for use with a bipolar return-to-zero receiver.
During a reset operation the gate of a reset transistor coupled to the storage node receives a voltage greater than a threshold voltage to produce a reset of the storage node.
Upon manual reset operation, the reset rod (14) can be engaged with the movable contact support (10) to move it up to a position for completing the reset operation.
Reset in case of memory overflow
Zeroing and calibration are also provided.
A push button on the computer system causes system reset, thereby causing the serial card to reset.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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