A selector receives the initial duty cycle and the linearized duty cycle and selects one of the initial duty cycle and the linearized duty cycle as a secondary duty cycle in response to the comparing.

Therefore an effective duty cycle is equal to a setpoint duty cycle.

The drive controller (16) adjusts the duty cycle to achieve the desired power unless the adjustment of the duty cycle causes the duty cycle to be outside of a predefined duty cycle range.

A linearization table converts the initial duty cycle to a linearized duty cycle.

The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent 10 on a duty cycle index value that it receives.

The controller sets the duty cycle to a preset duty cycle and adjusts the frequency to achieve the desired power if the adjustment of the duty cycle causes the duty cycle to be outside the predefined duty cycle range.

An offset is added to the secondary duty cycle to obtain and adjusted duty cycle.

The variable duty cycle circuit supplies a duty- cycle adjusted clock signal to a divider circuit.

A duty cycle circuit may measure the duty cycle of current flowing through one of the electronic switches.

Then its duty cycle is limited.

The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal fro m the maximum frequency.

A duty deflection calculation means (341) judges whether a duty deflection between the respective phases exceeds the duty deflection allowance value (Dth).

The amplifier circuit includes a duty cycle error measurement circuit which measures the error of the output signal from a predetermined duty cycle, for example, 50 % duty cycle.

The method includes obtaining a motor control signal (16) having an initial duty cycle and linearizing (3) the initial duty cycle to obtain a secondary duty cycle.

A duty threshold value input means (342) inputs an obtained duty deflection allowance value.