The invention relates the executing of computer readable instructions on a hardware platform (301) comprising a reconfigurable hardware component (311), such as a field-programmable gate array (FPGA).

An apparatus comprising programmable logic devices including a field programmable gate array (FPGA) is presented.

The system evaluates parse-trees using a field programmable gate array (FPGA) chip (122).

A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs).

To configure the field programmable gate array, the encrypted configuration data is decrypted by the security circuit (64) of the field programmable gate array using the security key stored in the field programmable gate array.

The configuration data is encrypted by a security circuit (64) of the field programmable gate array using a security key (62).

An FPGA is comprised of a number of cells which perform logical functions on input signals.

a microcontroller, in some versions; a microprocessor or field programmable gate array (FPGA), which processes the information and acts on the interface between the GPS;