A transistor structure (50) is provided comprising a source region (82, 86) having a N+ drain region (80) and a N' lightly doped drain region (80) and a N' lightly doped drain region (84).

The transistor structure having a source region, a drain region, a channel region between the source and drain regions, and a gate oxide on the channel region.

The narrow band gap material may be SiGe.

A source region (20), drain region (40), and a channel region (60) are formed in the substrate, with the drain region (20) spaced apart from the source region (40) and the gate region (30) abutting the channel region (60).

The image is separated into a source region and a target region.

A source region, drain region, and channel region are formed in the well.

A trench region (59) is formed between the source region and the drain region.

The source/drain region has a single source/drain structure.

Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region.

A gate region is disposed above the source region and adjacent the body region.

A channel region (17) is formed between the source region (14) and the drain region (14).

A static induction transistor having source, drain and gate regions.

Furthermore, the portion of the N-well generated beneath the source diffusion region produces a low-impedance path for the source region, which restricts the transistor current flow in between the drain region and the source region.

The kuark has a defined source region, or pattern, within the source context and a mapping between that source region and a defined destination region, or pattern, within the destination context.

The MOSFET has a first source/drain region (202), a second source/drain region (204), and a channel region (206) between the first and the second source/drain regions.