The active layer includes a gate region, drain region and source region.

A memory device (100) includes a semiconductor wire including a source region (132), a drain region (134), and a channel region (130) between the source region (132) and the drain region (134).

The transistor further includes a source region and a drain region.

The HEMT cap layer has a drain region, a source region, and a gate region.

The substrate includes a channel region situated between a drain region and a source region.

The transistor comprises a substrate region that includes a source region and a drain region.

The gate region is formed in a loop around the drain region.

The drain region is then formed in the cavity.

The fin structure serves as a channel between the source region and the drain region.

Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region.

In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions.

The body layer (201) has a drain region.

The channel region (CO) extends in a first direction (X) between the source region (12,S) and the drain region (12,D).

The drain region and the source region are formed asymmetrically with respect to the channel region.

The IGFET includes an N+ first drain region (6), an N- second drain region (7), a P first body region (8), a P- second body region (9), an N first source region (10a), and an N+ second source region (10b).