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électronique et électrotechnique - iate.europa.eu
électronique et électrotechnique - iate.europa.eu
électronique et électrotechnique - iate.europa.eu
A novel single-axis mems tilt sensor with a high sensitivity in the measurement range from 0∘ to 360∘... The structural design of the tilt sensor is optimized by finite element simulation and the device is microfabricated using a silicon-on-insulator process, followed by open-loop and closed-loop characterizations....
général - core.ac.uk - PDF: doaj.org
Asic implementation of time-domain digital back propagation for coherent receivers... Here, we implement time-domain DBP (TD-DBP) in a 28-nm fully-depleted silicon-on-insulator process technology, considering digital implementation aspects such as limited-resolution arithmetic and finite-length filters....
Design of dual ended tuning fork resonators for roller bearing micro- strain measurement...length.) Dual Ended Tuning Fork (DEFT) resonators fabricated in a Silicon-on-Insulator process are examined as strain sensors for this application using Euler-Bernoulli beam theory....
Fast piezoelectric scanning mems mirror for 1d ion adressing... The device is intended for higher frequency operation by reducing the scale of existing designs, and was fabricated using a multi-user silicon-on-insulator process....
électronique et électrotechnique - iate.europa.eu
Cmos silicon-on-sapphire rf tunable matching networks...0.5 m silicon-on-sapphire (SOS) CMOS technology was chosen for network implementation because of the relatively high-quality monolithic inductors achievable in the process....
général - core.ac.uk - PDF: doaj.org
Improved soi image sensor design based on backside illumination on silicon-on-sapphire (sos) substrateThe characteristics of phototransistors on silicon on sapphire (SOS) substrate were studied....
3d integrated sensors in silicon-on-sapphire cmos...0.5µm Silicon-on-Sapphire (SOS) process....
Laser annealing of silicon on sapphireSilicon-implanted silicon-on-sapphire wafers have been annealed by 50-ns pulses from a Q-switched Nd : YAG laser....

Publications scientifiques

A gate-level timing model for soi circuits †Abstract – Partially depleted floating-body (PDFB) SOI technology offers the potential of increased speed and lower power dissipation over traditional bulk CMOS....
électronique et électrotechnique / politique des transports - core.ac.uk - PDF: citeseerx.ist.psu.edu
Strong efficiency improvement of soi-leds through carrier confinementContemporary silicon light-emitting diodes in silicon-on-insulator (SOI) technology suffer from poor efficiency compared to their bulk-silicon counterparts....
métallurgie et sidérurgie / électronique et électrotechnique - core.ac.uk - PDF: purl.utwente.nl
Scattering mechanisms in mos/soi devices with ultrathin semiconductor layers, journal of telecommunications and information technology, 2004, nr 1Main scattering mechanisms a ecting electron transport in MOS/SOI devices are considered within the quantum-mechanical approach....
électronique et électrotechnique - core.ac.uk - PDF: dlibra.itl.waw.pl
History of semiconductors, journal of telecommunications and information technology, 2010, nr 1...the development of the first devices (point-contact rectifiers and transistors, early field-effect transistors) and the theory of semiconductors up to the contemporary devices (SOI and multigate devices)
électronique et électrotechnique - core.ac.uk - PDF: dlibra.itl.waw.pl
Capacitively-induced free-carrier effects in nanoscale silicon waveguides for electro- optic modulationWe fabricate silicon waveguides in silicon-on-insulator (SOI) wafers clad with either silicon dioxide, silicon nitride, or aluminum oxide, and by measuring the electro-optic behavior of ring resonators, we characterize...
électronique et électrotechnique / métallurgie et sidérurgie / chimie - core.ac.uk - PDF: emerald.ucsd.edu

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informatique et traitement des données / technologie et réglementation technique / industrie / énergie - iate.europa.eu
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