In a first embodiment, each cascode structure includes three gates (T1, T3, T5, T2, T4, T6) in series, the gates being controlled by the clock signal, a delayed inversion of the clock signal, and the data state or its inverse.

Two inductors are connected in series and are bridged by two valves that are connected in series.

The two resistors (8, 9) are connected in series.

Each of blocks includes the plural cells connected in series.

The resistors (10, 12) are connnected in series or in parallel.

At the end the sections are once again arranged in series.

The varistor and the PTC resistor are electrically connected in series.

The two rows of segments are staggered corresponding to the spacing of two series-connected photo diodes, or two series-connected groups of parallel connected photodiodes.

The array of series-connected LEDs has a turn- on voltage.

The inverter circuit comprises multiple power units connected in series.

The LED chip has an array of light emitting cells coupled in series.

All single coils (10, 11) of each coil group are electrically connected in series.

The blades (32) are mounted in a series of vertically spaced apart bays (14).

The two ports of the second diode are connected in parallel with the first switch tube, and the two ports of the forth diode are connected in parallel with the second switch tube.

The same concepts are applicable to series-connected coils.