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machine systolique

systolic loop architecture

informatique et traitement des données - iate.europa.eu

systolic architecture

informatique et traitement des données - iate.europa.eu

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Systolic architecture for adaptive censoring cfar pi detectorA new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adaptive censoring (RACPI) is presented in the paper....

général - core.ac.uk - PDF: citeseerx.ist.psu.edu

An efficient systolic architecture for the dlms adaptive filter and its applicationsAbstract—In this paper, we propose an efficient systolic architecture for the delay least-mean-square (DLMS) adaptive finite impulse response (FIR) digital filter based on a new tree-systolic processing element ( ) and an optimized...

PDF: citeseerx.ist.psu.edu

Synthesis of a new systolic architecture for the algebraic path problem... First, we informally explain how to derive this new systolic architecture, then we show how to synthesize it using a systematic methodology based upon uniform recurrence equations....

PDF: citeseerx.ist.psu.edu

Systolic architecture of adaptive post detection integration cfar processor in binomial distribution pulse jamming*... A new parallel algorithm for signal processing and a parallel systolic architecture of a CFAR processor with adaptive censoring and post detection integration (API) are presented in the paper....

PDF: www.iit.bas.bg

Designing systolic architecture for symmetrizing hessenberg matricesIn this paper, we describe a systematic method for mapping the problem of symmetrizing Hessenberg matrices onto systolic architectures....

PDF: citeseerx.ist.psu.edu

Publications scientifiques

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Design approach of the movie programmable video processor

... Le circuit MOVIE est une petite machine systolique composée d'un processeur d'entrée/sortie et d'un réseau linéaire de processeurs de calcul, il inclut les mécanismes adaptés à l'acquisition et à la restitution...

... Externally, the chip is provided with four bidirectional data ports andthree bidirectional data video port, allowing specialized parallel and programmable architectures of various configurations to berealized ...

Europe / politique tarifaire - core.ac.uk - PDF: core.ac.uk