Each cache line has multiple portions, and validity bits are used to track the validity of respective portions of the cache line.

When the requesting processor core makes repeated accesses to that cache line, it may be moved either between cache molecules or within a cache molecule.

If the tag of a particular set matches the address received by the cache memory, then the cache line associated with that particular set is the requested cache line.

The data array comprises multiple elements, each of which can contain a cache line.

The busy state and pending state cooperate to reserve a cache line for future use by a processor while the cache line is currently being used by one or more other processors.

If a cache line stores the memory address, it is flushed from the cache.

In one embodiment, a cache line brought in from memory may initially be placed into a cache molecule that is not closest to a requesting processor core.

The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core.

Indicator bits may be stored on a cache line basis to indicate the type of data is stored therein.

The contents of the affected cache line are not required to be a part of the answer.

The data cache is configured with a locking mechanism for each cache line stored in the data cache.

If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts.

The data processor (120) allocates a memory location to at least one cache line of the cache (124).

Each cache line contains a rehash block (18) indicating whether the set is a rehash location.

Each tag entry may be associated with a cache line from a cache belonging to a first domain.