The address generator can support multiple interleaving schemes.
The buffer structure includes a buffer and an address generator.
The storage system includes a plurality of storages, a shift generator, an address increment look-up table, an address shifter, a row address generator and a plurality of address adders.
The address generator (102) is operative to receive reconfiguration information.
The address generator provides addresses for writing symbols to the assigned sections.
The control state machine (520) includes a switch address generator (612) and a program counter select (616).
An aspect relates generally to an address generator (220) which has first and second processing units (310, 320).
The electronic circuits comprises: a memory (108), the address generator (102), and a Soft Input Soft Output decoder (106).
The local data address generator and programmable computational unit are configurable to cover any field requiring large computations.
A R/W control block (26), an address generator block (28), a data generator block (30) and a comparator block (32) are provided for communication with the memory (10) under test.
The address generator (102) is operative to reconfigure during operational use the interleaving scheme in dependency on the reconfiguration information.
The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.
An address generator is provided with features of suppression of power consumption, a simplified device structure, and a small installing area.
Signals (digital sine wave signals) (Sd) stored in a memory means (3) are read.
The address generator generates the address of the code table to be searched by adding the value of bits to be searched to a base address.
The switch address generator (512) outputs a switch address, which is an address for a first instruction for a selected-context instruction module.
The address generator is adapted to generate addresses for successive frames that are of variable length by skipping unused memory locations.
A second communication unit performs broadcast transmission to the client device, wherein a registration start notification which stores the secret address generator is transmitted.
In the programmable addressing block (410), an input address generator (442) has an input addressing microsequencer and an input addressing memory that stores an input addressing procedure.
The memory read address generator generates addresses dependant on a finger select value and a counter value.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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