utilization factor of the maximum capacity of a unit
plant utilization factor
The adjustment is based on a utilization factor of the PUCCH over a time period.
System efficiency and resource utilization factor could be improved.
This last utilization factor posits a position of influence for the analyst.
utilisation factor of the maximum capacity of a unit
This problem is solved in that the fields of lines of magnetic force are closely focused by an amorphous metal alloy, so that they cannot scatter; the scattering factor equals zero and the utilisation factor is doubled or tripled.
installation instructions for optimising the Utilisation Factor
The method comprises estimating a utilisation factor representing usage of the transmission intervals, and scheduling the data for transmission to increase the utilisation factor.
Utilisation Factor values for standard road conditions in tabular form for the defined road class.
The aim of the invention is to provide a cost-effective method for the ozone used, whereby said method has a high coefficient of utilisation and is based upon the known method.
The component use factor is low, and those component would gain to be multifunctional.
The embodiments of the present invention can enhance the transmission speed rate of the program and the use factor of the bandwidth.
The invention is characterized in that the first and second pulse duty factors are provided independent of one another in order to minimize the current passing though the low-pass filter.
The controller may compare the determined duty cycle against a duty cycle threshold.
At least one of the first duty cycle or the second duty cycle is greater than fifty percent.
In one embodiment, a duty cycle correction circuit matches the receiver clock to a predetermined duty cycle.
The receiver clock is then configured to have a duty cycle skewed from the predetermined duty cycle based on the specific data signal received.
A duty cycle control regulates a duty cycle of each buck stage to maintain the output voltage V0.
The duty factor decreases as supply voltage increases.
The beam control technique may be applied to wafer doping implantation and duty factor reduction.
The control circuit controls the plurality of switching elements so that width fluctuations related to the modulation of the duty factor are asymmetrical.
A radar system (25) and method for determining the range and, optionally, the azimuth of a target, while maintaining a high transmitting duty factor is provided.
In the first method, conventional pulse duration modulation produces a dimming ratio much greater than the ratio of duty factor variation.
This was done by multiplying the usage factor of each production factor by their undistorted cost per unit.
The pulse frequency, and duty cycle is controlled by a duty cycle control signal to modulate overall optical power and adjust amount of despeckle.
A duty cycle relationship is varied between the test signal and the timing signal used by the receiver of the system, and the effect of the duty cycle variation is analyzed.
At low dimming levels, the processor modulates the duty cycle or a first square wave for affecting the light level and maintains a minimal duty cycle of a second square wave.
A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received.
A controller is configured for determining duty cycle of a communication channel, and for controlling power level of the communication channel based on the determined duty cycle.
Disclosed is a duty cycle correction apparatus.
The corrector circuit generates a clock output signal with a corrected duty cycle.
Vibration magnitude is based on control signal duty cycle, and vibration frequency is based on control signal frequency.
On the basis of a target current value (x1) to be inputted, the outputted corrected current value (y4) and the outputting corrected duty (3d), the duty (d1) is computed, and the results are outputted.
The duty cycle of each driving signal is measured, and the difference (Δ) in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier (38A-38D).
A clock pulse duty cycle control circuit for receiving an input clock signal and for providing an output clock signal having a desired duty cycle.
The differential integrator integrates the output clock signal to produce a time-varying DC error signal representative of a difference between the output clock signal duty cycle and the desired duty cycle.
With the invention, the utilization rate of the system storage resources is improved.
The duty cycle control may be applied without using an energy storage device.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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