The present invention is mainly used for the generation of the phase discriminator clock.
A phase discriminator and a phase-locked loop circuit are disclosed.
The phase-locked loop comprises a phase discriminator, a loop filter and multiple voltage-controlled oscillators.
A phase discriminator produces a phase error output at the symbol rate from the phase error update based upon a signal modulation type.
The functions range from simple totalizing up to position display (with phase discriminator).
An improved phase detector for use in a phase-locked loop.
A non-linear phase detector includes a retiming stage (32) and a phase synchronization stage (34).
The PLL comprises a phase detector (402), a filter (404), a voltage control module (406) and an oscillator (408).
The second power supply device is connected with the output of a phase and frequency discriminator via an amplifier and a low pass filter.
The equipment includes a photographed object illumination intensity sensor (1 ) whose output is connected to an oscillating luminous wave phase detector (3).
Light reflected from the scale (10) passes back through the filter (26) and through the lens (16) to a phase discrimination circuit (41).
In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference.
The system includes a sampling and pretreatment device, an adaptive equalization filter, a phase discriminator, a loop filter and an oscillation device, which are connected orderly.
The phase discriminator (3), the saw-tooth generator (4), the double moving window comparison group (5) and the operation processing circuit (6) are connected in sequence.
A Complex Adaptive Phase Discriminator (PD), as presented in some concepts of the present disclosure, is an adaptive filter that accurately estimates the instantaneous frequency of a dynamic complex signal.
A phase discriminator (PD) and two frequency discriminators (FD1, FD2) are used for controlling said control loop.
A phase discriminator (340) compares output from each chain and feedsback a signal to one of the chains and to a comparator (230) and can equalize delay through each chain.
The invention relates to a clock and data regenerator that consists of a control loop.
The signal output ends of the measuring signal pre-process circuit (2) and the reference signal pre-process circuit (1) are connected with the signal input ends of the phase discriminator (3) respectively.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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