The delay can be converted into control settings such as sector delay, clock cycle delay and residual fractional delay settings that each represent a portion of the delay.

The delay pipeline may include a plurality of delay elements.

A transmission system (20A) reports delay information (S1info) related to the delay stream (S1delay) and delay information (S2info) related to the delay stream (S2delay).

The time delay encoding unit (405) encodes the frame time delay D.

The device further comprises a delay unit (4i).

A delay quality degradation estimation unit (12) estimates a delay quality degradation amount (23B) according to an audio delay time (22A) and a video delay time (22B).

The delay amounts of these variable delay circuits are set by a first delay adjustment unit (300).

The delay time is controlled by the delay time specifying signal of the delay time setting circuit (8).

The substrates are oriented so that their principle axes of retardation are orthogonal. nλ, is a base retardation of a waveplate and Δ λ, is an incremental retardation.

Delay is added using delay lines (360, 361).

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The delay unit controls a delay amount assigned to the data signal.

Each delay profile generating unit (101, 102) generates each delay profile from a reception signal at each antenna, and a delay profile adding unit (104) adds each delay profile to generate antenna synthesis delay profile.

A fine delay circuit latches the tap clock signals and develops a fine delay from the latched signals, and activates a fine delay enable signal having the fine delay in response to the coarse delay enable signal.

Each delay element may be a current-starved delay element.