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A high throughput hardware architecture for parallel recursive systematic convolutional encoders... Through an analysis of the proposed network topology and by exploiting data relative to the implementation on Zynq 7000 xc7z010clg400-1 field programmable gate array (FPGA), an estimation of the dependency of the input data rate and of the source occupation on the parallelism degree is performed....
général - core.ac.uk - PDF: doaj.org
Low-complexity high-throughput decoding architecture for convolutional codes... The relationship between the input data rate, the clockspeed of the decoder and the input buffer size can be easily established via the DTMC model....
Low-power design of a digital fm demodulator based...BT=0.3 GMSK input with an input data rate of 8000 bps and displayed a better BER Performance than coherent detectors....
High speed neural network chip for trigger purposes in high energy physics... The chip is optimized for a high input data rate (50 MHz, 16 bit data) at a very low cost basis....
Fractional rate phase detectors for clock and data recoveryAbstract — Some recent PLL designs utilize a half-rate phase detector so that the VCO operates at a frequency that is one-half of the input data rate....


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