The method for producing this PIN photodiode provides that a vertical structuring is effected on the series of layers in order to form lateral walls, whereby the intrinsic layer is exposed to permit light to strike the same.
Each of the structures comprises an intrinsic layer on one of an n type layer and a p type layer and the other one of the n type layer and the p type layer on the intrinsic layer.
The deep intrinsic layer belongs, as the name suggests, to the overall intrinsic layer.
An intrinsic layer (30) of semiconductor material is disposed between the first layer (20) and second layer (40).
The silicon layer stack includes an n-doped layer provided above the reflective electrode, an intrinsic layer provided above the n-doped layer and a p-doped layer provided above the intrinsic layer.
A photosensitive device and method includes a top cell (102) having an N-type layer, a P-type layer and a top intrinsic layer therebetween.
The modulator (10) includes an N-type layer (14), a P-type layer (18) and an intrinsic layer (16) acting as the waveguide (20).
The intrinsic layer is treated (412) with a plasma to form seed sites.
A photovoltaic device and method include a photovoltaic stack having an N-doped layer (112), a P-doped layer (108) and an intrinsic layer (1 10).
One of either the intrinsic region (28) or the intrinsic layer (40) is formed from crystalline silicon, and the other of either the intrinsic region (28) or the intrinsic layer (40) is formed from amorphous silicon.
A first tunnel junction layer is formed (414) on the intrinsic layer by growing microcrystals from the seed sites.
The invention relates to a PIN photodiode comprising a series of layers consisting of a first layer having a first type of conductivity, of an intrinsic layer, and of a second layer having a second type of conductivity.
The semiconductor includes a first active layer having a first conductivity, a second active layer having a second conductivity opposite the first conductivity, and an intrinsic layer separating the first and second active layers.
The receiver grid (1.7) is formed from a semiconductor stack (1.2), of a doped p-layer (1.2.1), an intrinsic i-layer (1.2.2) and a doped n-layer (1.2.3).
The method comprises depositing a n-i-p layer at a deposition rate of at least ten (10) Å/second for the a-SiGe:H intrinsic layer.
Alternatively, a hydrogen-containing plasma is used to treat an upper portion of the intrinsic layer prior to deposition of the n-doped semiconductor layer.
At a back side of the intrinsic amorphous silicon layer (7), an emitter layer (13) and a base layer (19) are provided, each of these layers covering neighbouring partial areas of the back surface.
An intrinsic layer, also comprising polycrystalline ZnTe, may reside between the n-type and p-type layers.
The p-i-n junction contains an intrinsic layer disposed between a p-type silicon-based layer and an n-type silicon-based layer, and the p-type silicon-based layer is in contact with the HWF buffer layer.
The SPIN device comprises a P+ region (108) and an N+ region (110) formed in an intrinsic (I) layer (106).
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Traduction Translation Traducción Übersetzung Tradução Traduzione Traducere Vertaling Tłumaczenie Mετάφραση Oversættelse Översättning Käännös Aistriúchán Traduzzjoni Prevajanje Vertimas Tõlge Preklad Fordítás Tulkojumi Превод Překlad Prijevod 翻訳 번역 翻译 Перевод