In one embodiment, a directory cache stores data corresponding to a caching status of a cache line.
The caching status of the cache line is stored for each of a plurality of caching agents in the system.
The virtual machine controls caching within the method cache of a separate result of at least one method of the application marked as cache capable.
The access server can cache the announcement in a caching unit associated with the access server on receipt of the caching indication and the announcement.
The invention concerns a cache manager (100) for managing the intermediate caching of segmented multimedia items.
The outside dimension from valve cover to valve cover
The outside dimension from valve cover to valve cover
The outside dimension from valve cover to valve cover
The outside dimension from valve cover to valve cover
The outside dimension from valve cover to valve cover
The cache memory system includes a cache memory including a plurality of cache memory lines and a dirty buffer including a plurality of dirty masks.
The present invention relates to a display apparatus for a studying mask and to a method for displaying a studying mask.
The hierarchical cache includes a first cache, a second cache, and the content library, where the first cache has a length based on an age of the second cache.
The cache memory (110) includes partitioned cache (120) and shared cache (115).
A cache controller (20) is provided for selecting those cache lines (6) in the cache (5), which are to be evicted from the cache (5).
A data cache of the processor is a one-level cache, wherein the one-level cache comprises a private data cache and a shared data cache.
The cache directory is in communication with the write cache and the at least one read cache.
Provided are a cache optimization method, a cache and a cache optimization system.
A cache directory is also provided to track cache lines in the write cache and the at least one read cache.
A cache controller may be configured to predict whether the first cache block stored in the cache memory is identified as a dead cache block based on a cache burst of the first cache block.
The cache memory system may include fully configurable caches, partially configurable caches, or a combination of configurable and dedicated caches.
In one embodiment, a cache subsystem includes a cache memory and a cache controller coupled to the cache memory.
The progressive cache includes caches arranged in an order from least finished cache elements to most finished cache elements.
The cache memory is typically called level two cache.
The cache can be a database cache.
The cache lines include a first cache line.
The apparatus comprises a first data cache, a second data cache, and cache logic.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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