The phase locked loop comprises both a digital coarse loop and an analog fine loop.

A clock recovery circuit including a digital locked loop is disclosed.

The output from the digital oscillator (11) is then fed back to an input of the digital phase locked loop (10).

The control within the PWM audio power amplifier (10) may include digital feed forward open loop control or may combine digital feed forward open loop control with analog negative feedback closed loop control to minimize distortion in the output signal.

The servo circuitry is comprised of a differential phase detector (420) and a digital phase-locked loop (436).

The invention presented herein is directed to a battery injection and loop supervision (BILS) system and method that can be used in the DSL environment.

The invention relates to a digital phase locked loop (PLL) 12 for demodulating an intermediate frequency signal.

Remote terminal (330) encodes a signaling bit that is transmitted over digital loop (340) to switch (335).

The digital phase-locked loop advantageously has an adjustable bandwidth based on the amplification value.

The multi-bit block assembly circuit includes an oversampler, a digital phase-locked loop and a byte synchronizer.

A digital loop filter circuit is connected to the outputs of the phase detector circuitry and has outputs thereof.

A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described.

Line unit (320) is located in remote terminal (330) which is connected to switch (335) by digital loop (340).

The outputs of the digital loop filter circuit are coupled, through a summing circuit, to the input of the oscillator circuitry.

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