The second conveying speed (v2) is greater than the first conveying speed (v1).

S = 0,1 · V + (X) · V2

The capacitance is charged to ~V2 when the voltage applied to the clock signal side of the first MOSFET toggles to ~V2, and OUT is increased to a voltage greater than V2 when the output of the delay circuit toggles to ~V2.

The voltages (V1, V2, V3) are set so as to satisfy a relation of V1 > V2 > V3.

The ratio of (v1/v2) is computed.

The difference between the Abbe number ν1 and the Abbe number ν2 (ν1 - ν2) is set to be a value greater than 10.

When this mistake is noticed, the new version of the schema, v2, says that v2:Dolphin is a rdfs:subClassOf v2:Mammal.

The AS1002T v2 and AS1004T v2 is factory loaded with ADM 3.1.

When the Abbe number with respect to the d-line of lens (L1) and lens (L2) is respectively v1 and v2, the conditional expressions (1) and (2) are satisfied.　(1) 10.0＜v2 - v1 (2) 40＜v2

When this mistake is noticed, the new version of the schema, v2, says that v2:Dolphin is a rdfs:subClassOf v2:Mammal.

The voltages Vs, Vd, and V3 and the pulse voltages V1 and V2 satisfy the relationship of Vs, Vd, V3 > V1, V2.

v1.v2 and v1 x v2 : Scalar product and Cross product of any two vectors v1 and v2.

v1.v2 and v1 x v2 : Scalar product and Cross product of any two vectors v1 and v2.

The voltages (Vs, Vd, V3) and the pulse voltages (V1, V2) satisfy the relationship of Vs, Vd, V3 < V1, V2.

These six inequalities are satisfied if and only if V2 = V3 and V2 = V3 + $300,000 ≤ V4 ≤ V2 + $500,000.