Binary arithmetic decoding processing is subject to pipeline processing.

Division information calculator processing and generator processing are executed using pipeline processing.

Techniques for performing IFFT pipelining are described.

Techniques for performing IFFT pipelining are described.

This invention aims at providing a pipeline processor capable of optimizing a pipeline processing, which has a simple construction and employs simple control method, and there is also provided a clipping processor using the pipeline processor.

An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction.

There are provided effective pipeline processing element architecture using data partitioning and scalable complex processing element architecture.

The present invention relates to a method and apparatus for pipelined processing of data.

A pipeline engine is operable to pipeline the mapped memory access requests for both read and write operations in accordance with a predetermined pipelining scheme.

An asynchronous circuit having a pipelined completion to achieve improved throughput with parallel registers (401a-402d) and completion logic (410-420) configured in a balanced binary or skewed binary way.

A pipeline register unit (21) does not outputs a signal representing that the pipeline stop signal is 1, so that the reading of the instruction code from the RAM (11) and the pipeline processing are not interrupted.

The present invention provides a 64-bit adder having 4 spatially pipelined, 16-bit adder blocks (310).

A set of data is divided into a plurality of blocks and operated by the pipelining processing of the arithmetic units.

Techniques are disclosed for processing a video stream to reduce platform power by employing a stepped and distributed pipeline process, wherein CPU-intensive processing is selectively performed.

A data ordering system for use with personal computers having data pipelining capability is disclosed.