The processor core (10) includes a memory (24), an instruction register (14), a register signal circuit, a register file (12), and an arithmetic logic unit (ALU).
The instruction register receives and holds stored address and data signals in response to the signals.
The system includes a power island register and an oscillation control register.
The cache memory includes: a control register indicating one or more ways among the N ways; control means for activating the way indicated by the control register; and update means for updating the content of the control register.
The diagnostic circuitry (20) includes a control register execution log (36) for receiving control store addresses from a control register (30) associated with an "EXECUTE + 1" stage.
The operation may be programming a control register (114) or reading a status register (115).
The control means limits at least replace of a way other than the active way indicated by the control register.
If the operation is to be performed, a gated clock signal is enabled to the control and status register.
In addition to the device and the shared external terminal, the system includes a command register that receives a plurality of command signals, and digital logic devices coupled between the external terminal and the command register.
Each of the digital logic devices receives a different clock signal and outputs one of the command signals to the command register.
The method performs an operation by an application on a CSR block is provided.
The command signals are controlled by a command register (20) and are output from the virtual addressing buffer only when an address match has been verified.
The command register (120) decodes a program suspend command and provides a suspend signal as an output.
A valid control register contains a first control value before all valid array entries are validated and a second control value after all valid array entries are validated.
The switching signal is asserted when a bit of a mixer control register is written to.
One or more bits are selected from a stream of bits based, at least in part, on a space control register value and a time control register value.
A current control register (58) receives a numerical value from one of the thermometer code registers (52).
A transistorized switch (203) controls the electrical current in the pair of transistors in response to signals from a control register (128) within the switching array.
At the accessing time by a program, the propriety of the access is decided on the basis of the control information set at the address and the information of the domain control register.
The specific function for a given pin is selected by the enable signal from the control register which selects the appropriate functional block upon appropriate command from the microcontroller.
A wireless device dynamically programs a control register for a command-chain driven DMA device.
The method includes: (a) reading the indicia of membership; and (b) operating the control register in accordance with the indicia of membership to effect decoupling in response to the control signal.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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