If an error cell is detected, the address thereof is registered in a first error address register (21) or a second error address register (22).
In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register.
If both address registers have a pending write, the last loaded address register is checked for a match against the current write address using the previous address register and the comparator.
The MAC address register stores the MAC address for the second protocol, were the MAC address is dynamically determined in the field and written to the MAC address register.
If no match signal is produced, the real address register (40) is provided with the contents of the buffer register (20).
A host processor triggers the register device to transfer information over the address bus to a register on the memory device.
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To synchronize execution of logic equations by multiple sequencers, all program memories are addressed by one common address register (3).
The control register, data register and address register can be programmed to configure the choice of test algorithm, bus width and memory size to be used for testing.
If, in response to an applied address, the address translator (30) provides a match signal, the corresponding real address from the random access memory (34) is applied to a read address register (40).
The CPU loads the task state from the first address register associated with the CPU and resumes the loaded task loaded.
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If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.
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The built in self test module comprises, a control register for determining the choice of test algorithm, data register for determining data bus width; and an address register for determining memory size.
The scheduling processor then retrieves the task state from the second address register by the scheduling processor and schedules the retrieved task for subsequent execution.
For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signal and provides a registered address signal.
The arrangement comprises a register arrangement (JBSR, JBER) defining the position of a digital buffer in the digital buffer memory (JBUM), an offset value, an address calculation arrangement and an operating address register (JBAR).
The maximum size of address space depends on the length of the address register on the CPU.
Voice interaction between an address book established on the intermediary server computer for a user and the authorized user occurs by operation of a matching utility.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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