A programmable resistance memory includes a volume of programmable resistance material formed between and coupled to two electrodes.

The OTP/MTP structure can be programmed in one of three states, a preprogrammed high resistance state, and a programmable low resistance state and a programmable very high resistance state.

The programmable resistance memory material may be a chalcogenide.

A method of programming a programmable resistance element.

More particularly, the invention relates to a two-terminal, non-volatile programmable resistor.

The method of programming allows the programmable resistance element to be used as a fuse.

For one embodiment of the vertical diode, a programmable resistor contacts the top portion (42) of the silicon plug (38) and a metal line (48) contacts the programmable resistor.

A programmable resistance memory element and method of forming the same is described.

Each memory cell (MC) comprises a selecting unit (T) and a programmable resistance (R).

A similar effect is achieved by providing the operating circuit with a programmable resistor circuit having a plurality of programmable resistance values.

In a programmable resistor embodiment, the value of the resistance selected by subsequent digital codes increases by a constant ratio.

A programmable resistance memory device in which power consumption for memory cell operation may be reduced.

The neuromorphic circuit further includes variable resistance material electrically connected to both the first drain and the second drain, where the variable resistance material provides a programmable resistance value.

The present invention relates to an electrical device (Fig. 6) having a programmable resistor (PR) connected in series to a punch-through diode (S).

In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude.