The high order bit data path (42) for processing the at least one high order input bit (40) and providing at least one high order output bit (54).

The most significant 8 bits of output of the adder (2) are input to the most significant 8 bits of the 9-bit input accumulator.

High-order dispersion correction (308) may also be included.

The input lines are individual bit lines that are paired together from the least significant bit to the most significant bit.

The predetermined portion may be the leading digits of the modulus, or split between the leading and trailing digits of the modulus.

A scaling resistor (21) is coupled between a least significant node conductor (7-3) of the MSB ladder section and a most significant node conductor (7-4) of the LSB ladder section.

The serial signal has contracted remainder data for one pixel, arrayed in the order from the high-order bit side to the low-order bit side or from the low-order bit side to the high-order bit side.

Thus, it is possible to expect that the difference can spread from the most significant bit to the least significant bit.

The processor may determine most significant bits (MSBs) of the POC value.

Basically, you send the most significant 4 bits first, and then the least significant 4 bits second.

In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory.

A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion.

The high order bit data path includes at least one exclusive or gate (52).

The output is for providing the at least one low order output bit (66) and the at least one high order ouput bit (64).

The digital input signal [102] is partitioned into a less-significant bit signal [108] and a more-significant bit signal [106].