The central processing unit has a cache with cache lines that are augmented by cache metadata.

Each cache line of an instruction cache and a data cache may have a tag containing a secure bit to identify a secure cache line or a non-secure cache line.

The terminal has a read cache mechanism in which a read cache driver saves cache data in a read cache area.

There is a plurality of cache sets of contact pads (102, 104) on the cache die (45), one cache set for each cache unit (46-70).

The processor typically modifies the cache data stored in the cache.

A cache device comprises a low-voltage operable cache (200) and a low-area cache (300) the type of which is different from that of the cache (200).

The cache can be configured into a buffer portion or a cache portion for faster cache accesses.

The apparatus comprises additional memory associated with the queue memory structure is configured to record an evict way of the cache requests for the cache.

A cache unit (142) caches the preview structure data.

  A cache status calculation unit calculates a cash usage status such as a memory access number, a cache hit rate, etc., per task.

The combined data/coherency cache includes a system cache with a number of entries.

A cache token ensures that the cache remains synchronized with the index.

In one embodiment, a cache subsystem includes a cache memory and a cache controller coupled to the cache memory.

The cache memory is typically called level two cache.

A cache entry of the one or more cache entries may be based upon a condition.