The present invention relates to a SRAM-cell assembly which includes for each memory cell six MOS transistors designed as vertical transistors, wherein said MOS transistors are mounted on the sides of grooves (G1, G2, G4).
An SRAM (100) includes a memory cell array (10) and peripheral circuits arranged to surround the memory cell array.
The cell array is divided into a plurality of memory cell blocks (120).
The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping.
A magnetic storage device comprises an array of magnetic memory cells (50).
In one aspect, an apparatus includes an array of photovoltaic cells.
An auxiliary cell array (2) is arranged to be connected to a word line of the side where a memory cell array (1) increases its bit line address.
A memory cell array comprising the memory cells of the present invention can be arranged in a matrix format.
A solar cell array is formed by directly fixing solar cell modules on a roof.
Radiant energy is emitted from said emitter (13b) to a photocell array (13).
Each DRAM includes an array of bit cells arranged in rows and columns.
A test cell is selected from an array of cells on the substrate (120).
Photocell array (13) has a series of photocells (13a) containing ceramic emitter radiators (13b) for distributing radiant energy to said photocells.
The auxiliary cell array (2) stores data of memory cells of the first bit line address (Y0) of the next work line address to a predetermined bit line address.
A rechargeable thin film microbattery cell array of at least four thin film microbattery cells is electrically connected together.
A memory device has an array of memory cells which are positioned in a first block and a second block.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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