The proportion of parasitic capacities present in field effect transistors (FET) (31-36) that configure the semiconductor switch blocks (210, 220) are reduced through the addition of capacitative elements (51-62).
The array structure includes a plurality of field effect transistors (FETs), where each FET has a gate structure.
The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs).
In another embodiment the sense electrodes are field effect transistors (FETs) with a floating gate.
Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided.
The device comprises a plurality of Field Effect Transistors (FETs) coupled to a common floating gate and an ion sensing layer exposed to the sample and coupled to the floating gate.
An apparatus includes a field-effect transistor (FET).
The present invention may be embodied as a device that is realized by forming the gate of a field-effect transistor (FET) from a ferromagnetic material, forming a so-called 'Ferromag-FET.'
A system and method are provided for driving a power field-effect transistor (FET).
The module includes two low-pass filters (LPF), two phase lines, an FET switch circuit having a field-effect transistor (FET), and two SAW filters.
Disclosed herein are a field-effect transistor (FET) , a ferroelectric memory device, and methods of manufacturing the same.
The detector may be a FET.
A first or primary field effect transistor ('FET') (620) is separated from a body contact thereto by one or more second FETs (632) that are placed electrically in parallel with the first FET (620).
A trench-gated field effect transistor (FET) is formed as follows.
An improved negative differential resistance field effect transistor (NDR-FET) is disclosed.
A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET.
A field effect transistor is formed as follows.
Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided.
In another variation this probe is the gate electrode of a field effect transistor (FET).
A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure.
The first FETs have their gates connected to one another and to the input.
The invention relates to FETs with stripe cells (6).
A field effect transistor (FET) includes a substrate, and a gate layer formed on the substrate.
Each switching unit (10) comprises a series capacitor (3) and an FET (4).
The active device may be of the bipolar transistor type or the FET (field effect transistor) type.
A simple method for increasing the dynamic range of a GaAs FET amplifier.
A first and second FETs are configured in a common-gate configuration.
A first capacitor is connected between the FET source terminal and a second capacitor is connected between the FET drain terminal and ground.
Each electronic switch includes at least one field effect transistor (FET) (70) and a bias network (72).
Each stage has a FET (402, 404, 406, 408) whose channel forms part of the current path.
To this effect, a narrowing of the tracks associated to a Smart FET has been designed.
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