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Publications scientifiques

Esd implantations for on-chip esd protection with layout consideration in 0.18- salicided cmos technology... The second breakdown current ( 2) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG)....
général - core.ac.uk - PDF: ir.nctu.edu.tw:443
High-voltage esd structures and esd protection concepts in smart power technologies... For high-voltage IC products based on smart power semiconductor technologies for industrial, power and automotive applications, design of effective and cost-efficient ESD protection...
général - core.ac.uk - PDF: eldorado.tu-dortmund.de
On-chip esd protection design for icsAbstract: This tutorial paper reviews the state of knowledge of on-chip ESD (electrostatic discharging) protection circuit design for integrated circuits....
général - core.ac.uk - PDF: citeseerx.ist.psu.edu
Investigation and design of on-chip power-rail esd clamp circuits without suffering latchup-like failure during system-level esd test... The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test....
général - core.ac.uk - PDF: ir.nctu.edu.tw:443
Assessment of esd threats to electronic components and esd control requirements... We propose new methods for the assessment of real electrostatic discharge (ESD) threats to electronic components in modern electronics manufacturing environment, where the devices are more sensitive...
général - core.ac.uk - PDF: citeseerx.ist.psu.edu

Exemples français - anglais

transport terrestre - techdico
informatique et traitement des données - iate.europa.eu
informatique et traitement des données - iate.europa.eu
informatique et traitement des données - iate.europa.eu
informatique et traitement des données - iate.europa.eu
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