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Nouveau : Traduire du texte avec ChatDico – 172 langues

Dictionnaire français - anglais

décade de comptage du type à décalage

twisted-ring counter

électronique et électrotechnique - iate.europa.eu
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On using twisted-ring counters for test set embedding in bist... It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for high-performance designs because it does not add any mapping logic to critical functional paths....
général - core.ac.uk - PDF: citeseerx.ist.psu.edu
C ○ 2001 kluwer academic publishers. manufactured in the netherlands. on using twisted-ring counters for test set embedding in bist ∗... It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for high-performance designs because it does not add any mapping logic to critical functional paths....
 PDF: citeseerx.ist.psu.edu
Built-in self testing of high-performance circuits using twisted-ring counters... Test patterns are generated by reseeding a twisted-ring counter....
 PDF: citeseerx.ist.psu.edu
Design and implementation of an on-chip test generation scheme based on reconfigurable run-time programmable and multiple twisted-ring counters ... Related work based on single fixed-order twisted-ring-counter design requires longer testing time to achieve high fault coverage and large storage space to store the seeds and the control data....

decade counter

électronique et électrotechnique - iate.europa.eu
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Mt324 interactive computer graphics course description & objectives:... Decade counter, shift registers & applications, familiarities with commonly available 74XX & CMOS 40XX series of IC counters....
électronique et électrotechnique - core.ac.uk - PDF: vignanuniversity.org

Johnson counter

électronique et électrotechnique - iate.europa.eu

shift-type decade counter

électronique et électrotechnique - iate.europa.eu

Publications scientifiques

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Low power 130 nm cmos johnson counter with clock gating technique... Therefore in this projectthe reduction of power consumption of Johnson Counter by using clock gating technique ispresented....
général - core.ac.uk - PDF: eprints.uthm.edu.my
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Design of low power tpg for bist using reconfigurable johnson counter... Regular technique for test design age includes in Reconfigurable Johnson Counter and LFSR which needs in relationship between's progressive test vectors....
général - core.ac.uk - PDF: matjournals.in
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Low power design of johnson counter using ddff featuring efficient embedded logic and clock gatingAbstract—In this paper, we have proposed a power efficient design of a 4-bit up-down Johnson counter by using Dual Dynamic Node Pulsed Flip-flop(DDFF) featuring efficient embedded logic module(DDFF-ELM) and then clock gating is incorporated in order to reduce ...
général - core.ac.uk - PDF: ijergs.org
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A modified test pattern generation architecture for fault detection in bist... The test patterns generated using Johnson Counter and Seed Vector lacks in fault coverage....
général - core.ac.uk - PDF: matjournals.in
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Multiple sic-tpg schemes: by implementing reconfigurable johnson counter and scalable sic counter... A reconfigurable Johnson counter and a scalable SIC counter are developed to generate a class of minimum transition sequences....
général - core.ac.uk - PDF: ijarece.org

Synonymes et termes associés français

compteur par dix

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décade

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compteur de décades

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compteur décadique

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compteur à décades

Exemples français - anglais

amélioration du comptage à coïncidence

coincidence counting enhancement
technologie et réglementation technique - iate.europa.eu


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