Provided is a reconfigurable circuit generation device which can generate a small-area reconfigurable circuit in a short time.
A reconfigurable circuit (51) provided inside the DMA controller has a reconfigurable combinational circuit (52) and configuration memory (53) for storing the configuration information on circuit.
A reconfigurable circuit having redundant reconfigurable clusters is described herein.
Provided is a dynamic reconfigurable circuit effectively utilizing a configuration memory.
This reduces the time required for testing the reconfigurable circuit.
The control device includes a host (2), having a server (20) and non-volatile memory (21),and a reconfigurable interface device (5) having a reconfigurable circui (40).
The image data processing circuits (12, 13, 16, 15) include a programmable stream processing circuit (13) and a reconfigurable circuit (18).
A reconfigurable circuit having communication resources configured to facilitate selective packet-oriented communications among reconfigurable resources is described herein.
A reconfigurable circuit including a heterogeneous mix of processing elements is configured to use variable packet sizes.
A reconfigurable circuit has a plurality of calculation elements including a first calculation element and a second calculation element.
A method of producing a reconfigurable circuit device for running a computer program of moderate complexity such as multimedia processing.
A reconfigurable circuit having primary function blocks with runtime built-in self- test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.
The reconfigurable circuit collects signals passed on the communication channel and reports back to the CPU circuit when data indicative of the first event type occurs on the communication channel.
A system and method for detecting corrupted configuration data stored in a configuration memory of a reconfigurable circuit are described herein.
The method also comprises programming a reconfigurable circuit for implementing the descriptor module onto an instantiated FPGA block coupled to the tester processor.
The non-volatile memory (21) stores firmwares for reconfiguring the reconfigurable circuit in accordance with each of the several optional fieldbus networks.
A passage part (24) for connecting the output from the reconfigurable circuit (12) with the input thereof is formed as a feedback path.
In one particular example embodiment, a circuit arrangement having a CPU circuit (120) communicates with another device over a communication channel (130, 132) while a reconfigurable circuit (100) monitors the communication channel.
In response to the command the programmable stream processing circuit (13) is programmed to perform the image stream based operation and configuration data is loaded into the reconfigurable circuit (16).
Provided is a reconfigurable circuit which includes a plurality of reconfigurable cells and modifies the configuration of the calculation processing unit contained in each of the reconfigurable cells.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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