The excitation circuit (10) includes a NAND circuit (L1), and first and second inverters (L2, L3) which are dependently connected.
A very fine-grained gate array cell is provided that includes a two-input logic device and a cascade NAND gate with buffered output.
A gate of the load PMOS transistor is controlled by an output of a not- AND (NAND) circuit (106).
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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