The PMOS stage includes a first PMOS transistor (114), a second PMOS transistor (128), a third PMOS transistor (116) and a fourth PMOS transistor (126).

The n-channel FET has an n-channel width.

Each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node.

p-channel junction field-effect transistor

When the voltage between p-channel MOSFET (32) and resistor (42) reaches the threshold of an n-channel enhancement mode MOSFET (48), the p-channel MOSFET (32) is switched off.

The p-channel JFET of the example according to figure 1 is replaced by a normally on p-channel MOSFET and the n-channel JFET by a normally on n-channel MOSFET.

The drain of the first PMOS transistor is electrically coupled to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is electrically coupled to the drain of the second NMOS transistor.

One comparator is an N-channel device (N39), and the other comparator is a P-channel device (N36).

The source and drain of the second PMOS are connected to the first and second power source lines through fifth PMOS and sixth NMOS, respectively.

As a result, the amount of current injected into the first P-channel MOS transistor (MP32) is more precisely mirrored into the second P-channel MOS transistor (MP33).

It is beneficial for the integrated circuit (10) for the P channel SRAM transistors (26) to have a lower mobility than the P channel logic transistors (22).

Source and drain regions may be formed in the PMOS n-well (inversion mode) or the PMOS n+-doped contact may be formed in the PMOS n-well instead of being separated from there (accumulation mode).

The gate of the first PMOS transistor and the gate of the second PMOS transistor are electricalIy coupled to an inverted version of the latch input.

The circuit comprises three p-channel MOS transistors and three capacitors.

On an insulating layer (12) formed on a silicon substrate (10), an NMOS transistor (14) is formed in an NMOS transistor region (16) and a PMOS transistor (18) is formed in a PMOS transistor region (20).