A timing signal generator (10) adjustably times successive pulses of an output timing signal (TIMING-).

The oscillator controls clocking of the transceiver.

As a result there is no need for separate pulse lines and pulse circuits.

The electronic device may tag the timing elements with their type and may flag certain timing elements as being native to the display.

The method comprises using an analytical model comprising a timing estimator and estimating timing information of the processor.

Furthermore, the memory controller (10) has a delay circuit (13A) for adjusting the output timing of the received timing signal.

When the count value equals the known value, clocking by a second clock signal (COMP SYNC) is enabled.

A fine timing method is provided.

A timing module determines a duration of the first signal.

This method allows synchronization with an imprecise timing reference.

The method (200) comprises using an analytical model comprising a timing estimator (740) and estimating timing information of the processor.

The electronic device may automatically use a selected one of the filtered timing elements in displaying information on the external display.

A location (90) is provided for indicating the beginning of a timer list of processes awaiting execution and means (68) is provided for indicating the end of a timer list.

The first receiver is configured to produce an indication of a timing of the first signal.

The timing of this signal is not dependent upon the clock signal.