The invention relates to an RS flip-flop and to an RS flip-flop provided with a clock input, and to a frequency divider to be implemented therewith.

A set-reset flip-flop of all-optical operation.

Said output clock signal is provided at an output of the RS flip flop.

The junction gate has a function to acquire and hold the output by use of an RS-FF (FF of a reset-set input type) only when the output or input signal changes.

An RS flip-flop FF1 is set in response to a set pulse SP which passed through a set delay circuit (12).

The truth table in Figure 5 shows how the RS flip-flop operates.

Consequently, the SR flip-flop (14) is reset, and the level of an output C4 changes from high to low.

Each tachymetric pulse energizes the input (R) of the flip-flop RS (1), thereby preventing the driving pulses to reach the electric motor (3).

Once the system is switched to this operation mode, the R-S flip-flop (44) keeps this operation mode even after the ID card is pulled out from the card holder (4).

The input (S) of this flip-flop RS (1) is connected to the output of the first AND gate (7) while the output of the second AND gate (8) is connected to the input (R) of the flip-flop RS (1).

A differential SR flip-flop (100) generates a differential output pair (Q, #Q) upon receiving a set signal (S) and a reset signal (R).

The apparatus also includes a set reset flip-flop having a set input adapted to receive the first and second binary signals to provide a third binary signal.

  The differential SR flip-flop (100) outputs a signal corresponding to the first output signal (Q3) and a signal corresponding to the second output signal (#Q3) as the differential output pair.

Embodiments utilize output driver buffers internal to the RS flip-flop circuit configuration provides oscillator feedback delay.

Furthermore, a third and fourth inverter (1 and 2) are connected ahead of the RS flip-flop (RS_FF), so that the input of each inverter constitutes a clock input (CLK).