The BTAC is indexed by a truncated branch instruction address.
The processor may initialize hardware loops in the user mode by loading a top instruction address in LOOP_TOP register and a bottom instruction address in a LOOP_BOT register.
In this technique, a branch target address is retrieved from the BTAC in response to a miss in looking up an instruction address in an instruction cache (I-cache).
The apparatus includes a first input which is configured to receive an instruction address and a second input.
When the same instruction address is associated with more than one data address, the difference between the two data addresses is recorded.
On the read operation, one instruction address may be read from a top register, and the contents of each register may be shifted one register upstream.
A method includes generating (304) an instruction address value in response to an instruction source event (302).
The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units.
The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output.
The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame.
A hypervisor (1) judges that the same instruction address is continued for each of two CPUs of a guest OS (2) for a predetermined period of time.
In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.
The central operation means (105) analyzes the contents described at an instruction address in the storage means (101) and performs various types of operation processing, at each predetermined operation unit clock.
If judging that the same instruction address has been continued for each of the two CPUs for the predetermined period of time, the hypervisor (1) estimates the occurrence of a deadlock in the guest OS (2).
The branch target address is associated with the instruction address.
Requêtes fréquentes français :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
Requêtes fréquentes anglais :1-200, -1k, -2k, -3k, -4k, -5k, -7k, -10k, -20k, -40k, -100k, -200k, -500k, -1000k,
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